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ADT7490
Table 109. REGISTER 0x90 ? DYNAMIC T MIN CONTROL REGISTER 3 (POWER-ON DEFAULT = 0x00)
Bit No.
[2:0]
[5:3]
[6]
[7]
Mnemonic
RES
CYP
PHTP
PECI
R/W (Note 1)
Reserved
R/W
R/W
R/W
Description
Reserved
3-bit PECI Temperature Cycle Value. These three bits define the delay time between making
subsequent T MIN adjustments in the control loop for the PECI temperature channels in terms
of number of monitoring cycles. The system has associated thermal time constants that need
to be found to optimize the response of fans and the control loop.
Bit Code
Decrease Cycle
Increase Cycle
000
8 cycles (1 sec)
16 cycles (2 sec)
001
16 cycles (2 sec)
32 cycles (4 sec)
010
32 cycles (4 sec)
64 cycles (8 sec)
011
64 cycles (8 sec)
128 cycles (16 sec)
100
128 cycles (16 sec)
256 cycles (32 sec)
101
256 cycles (32 sec)
512 cycles (64 sec)
110
512 cycles (64 sec)
1024 cycles (128 sec)
111
1024 cycles (128 sec)
2048 cycles (256 sec)
PHTR1 = 1 copies the PECI0 current reading to the PECI operating point register if THERM
is asserted. The operating point contains the temperature at which THERM is asserted,
allowing the system to run as quietly as possible without affecting system performance.
PHTR1 = 0 ignores any THERM assertions on the THERM pin. The PECI operating point
register reflects its programmed value.
PECI = 1 enables dynamic T MIN control on the PECI temperature channel. The chosen T MIN
value is dynamically adjusted based on the current temperature, operating point, and high
and low limits for this zone.
PECI = 0 disables dynamic T MIN control. The T MIN value chosen is not adjusted and the
channel behaves as described in the Automatic Fan Control Overview section.
1. This register becomes read-only when the Configuration Register 1 (0x40) Lock bit is set to 1. Any subsequent attempts to write to this
register fail.
Table 110. REGISTER 0x94 ? PECI0 TEMPERATURE OFFSET (POWER-ON DEFAULT = 0x00)
Bit No.
[7:0]
R/W (Note 1)
R/W
Description
Allows a temperature offset to be automatically applied to the PECI0 channel measurements. The
programmable offset range is from ? 63 ? C to +127 ? C with 1 ? C resolution.
1. This register becomes read-only when the Configuration Register 1 (0x40) Lock bit is set to 1. Any further attempts to write to this register
have no effect.
Table 111. REGISTER 0x95 ? PECI1 TEMPERATURE OFFSET (POWER-ON DEFAULT = 0x00)
Bit No.
[7:0]
R/W (Note 1)
R/W
Description
Allows a temperature offset to be automatically applied to the PECI1 channel measurements. The
programmable offset range is from ? 63 ? C to +127 ? C with 1 ? C resolution.
1. This register becomes read-only when the Configuration Register 1 (0x40) Lock bit is set to 1. Any further attempts to write to this register
have no effect.
Table 112. REGISTER 0x96 ? PECI2 TEMPERATURE OFFSET (POWER-ON DEFAULT = 0x00)
Bit No.
[7:0]
R/W (Note 1)
R/W
Description
Allows a temperature offset to be automatically applied to the PECI2 channel measurements. The
programmable offset range is from ? 63 ? C to +127 ? C with 1 ? C resolution.
1. This register becomes read-only when the Configuration Register 1 (0x40) Lock bit is set to 1. Any further attempts to write to this register
have no effect.
Table 113. REGISTER 0x97 ? PECI3 TEMPERATURE OFFSET (POWER-ON DEFAULT = 0x00)
Bit No.
[7:0]
R/W (Note 1)
R/W
Description
Allows a temperature offset to be automatically applied to the PECI3 channel measurements. The
programmable offset range is from ? 63 ? C to +127 ? C with 1 ? C resolution.
1. This register becomes read-only when the Configuration Register 1 (0x40) Lock bit is set to 1. Any further attempts to write to this register
have no effect.
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